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Personally I don’t assume we'll see the road between memory and storage be all that muddled sooner or later. Yes, 3D XPoint is a lot more responsive than Flash. But Flash isn’t all that impressive as is. The standard onerous drive has entry latencies round 4ms on common. Flash can attain properly bellow µs latency, however for very small arrays. That is costly and largely seen in Microcontrollers that execute immediately from their Flash. "Enterprise grade" flash that optimizes at price/GB could have far larger latency, in the few to tens of µs region. 3D Xpoint is a little bit of a wash. I've seen quoted figures of sub 350ns write latency, but that is likely for a single cell, not an array. Optane modules from Intel on the other hand have typical latencies round 5-15µs, but that is from a "system" perspective, ie, protocol and controller overhead comes into play, in addition to one’s software program atmosphere.

DRAM then again has entry latencies round 2-15ns at current. The problem with latency is that it results in our processor stalling attributable to not getting the info in time. One can prefetch, however branches makes prefetching harder, since what facet do you have to fetch? Department prediction partly solves this situation. But from a performance standpoint, we should fetch each sides. But when now we have more latency, we have to prefetch even earlier, risking more branches. In other words, peak bandwidth required by our processor will increase at an exponential rate compared to latency. A rate that is application dependent as properly. Caching may appear like the trivial solution to the difficulty, but the efficiency of cache is proportional to the latency. To a level, cache is a magic bullet that just makes memory latency disappear. However each time an software requires something that isn’t in cache, then the applying stalls, as long as there's threads to take its place that even have information to work on, then you definately won’t have a efficiency deficit other than thread switching penelties, Memory Wave but in case you don’t have such threads, then the CPU stalls.
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One can be certain that extra threads have their data by simply making the cache greater, however cache is quite a bit more expensive than DRAM. In the end, it all results in the truth that rising latency would require an arbitrary amount extra cache for an analogous system efficiency. Going from the few ns latency of DRAM to the couple of µs latency of current persistent memory is not realistic as an precise replacement for DRAM, even if it reduces its latency to a 100th it remains to be not impressive as far as memory goes. Though, the usage of persistent DIMMs for storage caching or as a "RAM drive" of sorts still has main benefits, however for program execution it is laughable. And i don’t suspect this to change any time quickly. However I can see a future the place the primary memory relocates into the CPU. The place the CPU itself has an HBM Memory Wave Program chip or 4 on it supplying relatively low latency and high bandwidth memory to the CPU, while the exterior buses are used for IO and storage. But this isn’t all that life like in additional skilled purposes, since some workstation applications honestly needs 10’s-100’s of GB of precise RAM to get good efficiency.

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